1. Field of Invention
The present invention relates in general to mixed analog and digital signal processing and in particular, to synchronous sample rate conversion circuits and methods.
2. Background of Invention
In many applications, converting data from its native analog form into the digital domain for processing, storage and transmission provides the best overall system performance. One well known example is audio processing where analog audio is digitized through analog to digital (A/D) conversion and then processed, for example filtered or compressed, and then stored on a digital storage medium such as a compact disk (CD) or digital video disk (DVD). On playback, the digital data is decompressed, as required, reconverted to analog through digital to analog (D/A) conversion, and finally presented to the end user as audible tones.
According to the Nyquist Theorem, so long as the analog waveform is sampled during A/D conversion at a sampling frequency at least twice as high as the highest frequency component, that waveform can be successively reconstructed during subsequent D/A conversion. In actual practice, oversampling A/D and D/A converters are typically used because of their relative ease in implementation. For example, in an 8xc3x97 oversampling converter operating on data with a base sampling rate of 44.1 kHz, the data are sampled at a rate of 352.8 kHz. At the higher sampling rate, operations such as anti-aliasing filtering are easier since a substantial amount of the noise power is translated to frequency bands well above the band of the signal of interest.
Sample rate conversion is an additional problem which must be addressed when processing digitized analog data. For example, professional digital audio is typically recorded with a sampling rate of 48 kHz while typical playback devices operate with a base sampling rate of 44.1 kHz. Sample rate conversion, and specifically down-conversion, is therefore required to ensure that the recorded audio properly plays back. There are several existing sample rate conversion techniques, including decimation for lowering the sampling rate and interpolation for increasing the sampling rate. Notwithstanding, these techniques are still subject to some significant disadvantages including the need for substantial silicon area for fabricating the requisite interpolation/ decimation filters, as well as limitations on the ability to convert to fractional sampling rates.
The present principles are embodied in circuits and methods for providing accurate, synchronous sample rate conversion. According to one particular embodiment, a sample rate converter is disclosed which includes a filter for processing digital data in response to a clock controlled by a clock enable signal, the filter receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. A resampler generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate and, selectively, second selected periods of the clock enable signal having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.
Synchronous sample rate conversion circuits and methods embodying the inventive principles require substantially fewer filter stages and consequently can be implemented on substantially less silicon area. Moreover, such circuits and methods can be used in a wide range of synchronous applications including up-conversion (interpolation) and down-conversion (decimation). By appropriate selection of the operating parameters, fractional sample rate conversions can be accomplished.